1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device employing a refractory metal silicide layer as an electrode.
2. Description of the Related Art:
Hereinbelow is explained, with reference to FIGS. 1A to 1F, a conventional method of fabricating a semiconductor device employing a titanium silicide layer as an electrode. A semiconductor device described hereinbelow is of n-channel MOS type.
First, as illustrated in FIG. 1A, there are formed silicon dioxide films 2 having a thickness of about 300 nm at a surface of a p-type silicon semiconductor substrate 1. The silicon dioxide films 2 act as device isolation regions between which are defined device formation regions where a device is to be established. Then, ion implantations are carried out over the device formation region to thereby form a gate oxide film 3 having a thickness of 10 nm over the device formation region and further a polysilicon film 4 having a thickness of about 150 nm over the gate oxide film 3. Then, the gate oxide film 3 and the polysilicon film 4 are patterned by means of photolithography and reactive ion etching to thereby form a layered structure 3a which will make a gate electrode.
Then, as illustrated in FIG. 1B, phosphorus (P) ion implantation is carried out to thereby form lightly doped source and drain regions 5-1 and 5-2 in self-aligned fashion with the patterned polysilicon film 4. Then, a silicon dioxide film having a thickness of about 100 nm is deposited over a resultant. An anisotropic reactive dry etching is carried out to the thus deposited silicon dioxide film to thereby form an insulating spacer 6 around the layered structure 3a. Then, a resultant is implanted, for instance, at 30 KeV with doses of 3.times.10.sup.15 cm.sup.-2 arsenic (As) to thereby form highly doped source and drain regions 7-1 and 7-2 at regions other than the patterned polysilicon film 4, the insulating spacer 6 and the device isolation regions 2.
Then, as illustrated in FIG. 1C, a resultant is implanted, for instance, at 30 KeV with doses of 3.times.10.sup.14 cm.sup.-2 arsenic (As) to make a surface of the silicon substrate 1 amorphous. After a naturally oxidized film is removed, sputtering is carried out to thereby deposit a titanium film 8 having a thickness of about 30 nm over the substrate 1.
Then, as illustrated in FIG. 1D, first lamp anneal is carried out to a resultant at 690.degree. C. for 30 seconds in nitrogen atmosphere to thereby cause the titanium film 8 and the highly doped source and drain regions 7-1 and 7-2 to react with each other and also cause the titanium film 8 and the polysilicon film 4 to react with each other. As a result, as illustrated in FIG. 1D, there are formed titanium silicide layers 9 on both the polysilicon film 4 and the highly doped source and drain regions 7-1 and 7-2. By the first lamp anneal, the titanium layer 8 is converted to a layer 8a containing nitrogen, oxygen and titanium not having reacted with silicon. As illustrated in FIG. 1D, the layer 8a does not exist on the insulating spacer 6. By the first lamp anneal, there is further formed a denaturated layer 10 over the titanium layer 8a. Herein, the denaturated layer 10 is a layer made of the titanium layer 8 having reacted with both nitrogen and oxygen residual in the nitrogen atmosphere.
Then, as illustrated in FIG. 1E, the titanium film 8a is removed by means of a solution containing ammonia (NH.sub.3) and hydrogen peroxide (H.sub.2 O.sub.2), followed by second lamp annealing at 840.degree. C. for 30 seconds to thereby form a titanium silicide layer 9a having a smaller resistance than the titanium silicide layer 9. The titanium silicide layers 9 and 9a mainly contain crystal forms C49 and C54, respectively.
Then, as illustrated in FIG. 1F, a silicon dioxide film 11 is deposited by about 1 .mu.m over a resultant. Contact holes 12 are formed above the highly doped source and drain regions 7-1 and 7-2. Then, there is formed a barrier film 13 made of titanium and titanium nitride over an inner wall of the contact holes 12 by sputtering. Then, the contact holes 12 are filled with tungsten (W). Then, an aluminum film is formed all over a resultant, and patterned into a desired pattern to thereby form a wiring layer 15. Finally, a resultant is entirely covered with a cover film 16 made of silicon nitride.
The reason why the first lamp anneal for forming the titanium silicide layer 9 is carried out in nitrogen atmosphere is to prevent the titanium silicide layer 9 from growing horizontally from the titanium-silicon contact area to thereby deteriorate isolation between the gate electrode and the source/drain regions 7-1 and 7-2 and between wirings formed on the device isolation regions 2 such as word lines in a memory and the source/drain regions 7-1 and 7-2 in a MOS transistor. However, even this technique is not sufficient to prevent occurrence of current leakage. The reason is as follows. A rate for etching the denaturated layer 10 is quite small. Hence, it is not possible to sufficiently remove titanium when the denaturated layer 10 and the titanium film 8a are removed. As a result, electrically conductive materials leave non-removed at a surface of the insulating spacer 6 and the device isolation regions 2. Such electrically conductive materials deteriorate the isolation between the gate electrode and the source/drain regions and between wirings and the source/drain regions to thereby induce current leakage.
Japanese Unexamined Patent Publication 3-116837 has suggested a method for preventing occurrence of current leakage accompanied with the formation of a titanium silicide layer. In the suggested method, after the formation of the titanium film 8 as illustrated in FIG. 1C, a photolithography step is carried out to thereby form a mask out of a photoresist film on the titanium film 8 in a region other than regions such as the device isolation regions 2 and the insulating spacer 6 onto which a silicide layer is not allowed to grow. Then, oxygen ions are implanted into the titanium film 8 through regions not covered with the mask. Thus, oxygen ion implanted portions of the titanium layer 8 prevent silicon diffusion therebeyond during thermal annealing for converting a titanium layer into a titanium silicide layer.
However, the above mentioned method suggested in No. 3-116837 has shortcomings as follows. First, an additional photoresist step has to be carried out for forming the mask. Second, taking into consideration that a width of the insulating spacer 6, namely a width of a silicon dioxide film is quite small, and that it is difficult to avoid misregistration in pattern overlapping, it is quite difficult or almost impossible to form a silicide layer all over source/drain regions and a gate electrode, and hence the method disclosed in No. 3-116837 is not suitable for fabricating a semiconductor device in a smaller size and in higher integration.